1. Field
One or more embodiments described herein relate to a data storage circuit.
2. Background
Many electronic devices are controlled to enter a reduced power mode when, for example, there has been a period of inactivity. These modes not only prolong battery life, they also allow power to be used more effectively. For example, in a low power mode (e.g., power-down or idle mode), battery voltage may be diverted to maintain operation of only a few core functions of the device.
In mobile and other applications, a controller may adjust a logic circuit to operate in a low power mode. In this mode, external signals are required to be generated in order to retain storage of data at I/O pads and/or other locations in a circuit. The need to receive external (e.g., off-chip) signals for data retention adds to the number of control pins required for the device and also reduces power control efficiency and serves to deplete battery life. Even in applications where external signals are not generated on chip, improvements are still required for performing I/O data retention operation.